1. Field of the Invention
This invention relates generally to testing a semiconductor wafer. More particularly, the present invention relates to stressing semiconductor die configured in wafer form during burn-in testing.
2. State of the Art
Processed semiconductor wafers typically include an array of identical, substantially isolated circuitry, each of which is individually referred to as a “die” and also commonly referred to as a “chip.” Each semiconductor die includes specific circuitry for performing an integrated function. One common type of integrated circuit includes memory circuits for storing and retrieving information.
While many chips may be formed on a semiconductor wafer, not all chips formed on a semiconductor wafer operate in an acceptable manner, resulting in a “yield” of operable chips of less than 100%. Accordingly, individual dice must be tested to identify acceptably functional ones from inferior or even inoperable ones. A conventional test procedure for identifying functional dice occurs following the fabrication of an entire wafer of dice having a protective or passivation layer thereon. The protective passivation layer is then selectively removed to reveal or expose bond pads on the individual die which correspond to inputs and outputs of the integrated circuit. Once the bond pads are exposed, the semiconductor wafer is subjected to test probing whereby the individual dice are tested for satisfactory operation.
Inoperable dice are identified and noted, whereupon the semiconductor wafer is segmented or “singulated” into individual dice and segregated according to the previous test results. The acceptable or functional individual dice are assembled into final packages with the packaged dice being loaded into burn-in boards which comprise printed circuit boards having individual sockets for receiving the packaged parts. The populated burn-in boards are then placed into burn-in ovens whereupon the packaged dice are subjected to burn-in testing. Thereafter, the packaged dice are retested for functionality and further resorted into acceptable functional packaged dice and unacceptable or inoperative packaged dice.
As noted, a conventional burn-in test occurs on packaged parts which are then placed into sockets on a burn-in board. Such segmenting of the individual dice from a wafer-level configuration followed by the associated packaging of such parts may result in an appreciable increase in volume and dimensions for the testing of each die. Such a testing constraint results in a diminished number of semiconductor dice that may be subjected to burn-in testing during a single burn-in test sequence. To overcome such a shortcoming, wafer-level burn-in testing would be desirable, wherein a probe card having contact pins corresponding to the exposed bond pads for each of the dice on a semiconductor wafer may be coupled. While such an arrangement could be theoretically designed, such an arrangement is prohibitive and impractical due to the ever-increasing reduction in dimensions associated with the integrated circuits located on an individual die and the complexity and abundance of bond pads. Furthermore, the practicalities of forming a reliable connection with each of thousands of microscopic bond pads quickly becomes a reliability concern as well as an economic issue.
As a further matter of practicality, one aspect of electronic packaging includes formation of a multi-chip package wherein a plurality of semiconductor dice are placed and conductively coupled in a single package. Burning-in individual die prior to placing them in higher assemblies is clearly desirable. By way of example, the yield of a functional multi-chip module or package is a product of the overall yields of each of the components. Therefore, the yield of a multi-chip module formed from unburned-in parts is dramatically reduced by the use of semiconductor dice that have not been previously stressed and screened prior to packaging.
Additionally, burning-in semiconductor dice at a wafer-level accommodates the use of higher burn-in temperatures that are outside the specifications of the packaging material of conventional packages. Also, cost reductions are further manifest through economic efficiencies associated with scrapping packages associated with inoperative semiconductor dice and the related packaging labor.
As another matter of practicality, many integrated circuit customers acquire individual unpackaged dice for integration into higher level assemblies without relying upon an interface as provided for by the packaging of an integrated circuit die. While individual package dice have conventionally been subjected to burn-in testing to identify and dispose of inferior ones, the reliable culling of burn-in stressed unpackaged dice has remained elusive. Notwithstanding, customers maintain an expectation of quality in unpackaged integrated circuit dice as they have come to expect in burn-in stressed packaged integrated circuit dice. Therefore, it would be desirable to provide a method and system for stressing unpackaged integrated circuit dice during burn-in testing in order to segregate acceptable functional integrated circuit dice from inferior ones.